# Making Memory Chips Faster by Splitting Internal Wires > This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. - **Patent:** US 12740066 - **Original title:** Split memory array to reduce bit-line capacitance - **Granted:** 2026 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, consumer_electronics, telecommunications ## What it does This patent describes a way to improve memory performance by splitting a memory array into two or more smaller sections, called subarrays. It uses special electronic switches, called bit-line multiplexers or selection circuitries, to divide the bit-line routes between these subarrays. By decoupling the bit-lines in this manner, the electrical charge-storing ability, known as capacitance, on the bit-lines is significantly reduced. This reduction comes from decreasing unwanted parasitic capacitance and ensuring that a single bit-line doesn't have to power all the tiny switches (access transistors) in a memory row. For example, when reading data from a specific memory cell, only the relevant split bit-line segment is activated, allowing the electrical signal to develop faster and stronger, which leads to quicker data sensing and overall higher memory performance. ## What it does NOT cover - Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting. - Does not cover methods for reducing memory capacitance that do not involve splitting bit-lines with selection circuitries. - Does not cover improvements to memory speed achieved solely by optimizing access transistor switching without modifying bit-line architecture. - Does not cover memory architectures that do not rely on bit-lines for data transfer to and from memory cells. ## The clever bit The clever bit is the specific approach of actively decoupling bit-lines into separate routes using multiplexers. This allows for a targeted reduction of parasitic capacitance, ensuring that the main bit-line only drives a smaller portion of the memory array at any given time, which significantly speeds up signal development and sensing. ## Real-world examples 1. Dynamic Random Access Memory (DRAM) modules in computers 2. Static Random Access Memory (SRAM) caches in processors 3. NAND flash memory in solid-state drives (SSDs) 4. Embedded memory in system-on-a-chip (SoC) designs ## Why it matters The speed of memory directly impacts how fast computers, phones, and other devices can operate. This patent addresses a fundamental physical limitation in memory design: the parasitic capacitance on bit-lines that slows down data access. By reducing this capacitance, the technology described could lead to faster, more power-efficient memory components, which are crucial for everything from high-performance computing to everyday consumer electronics. ## Frequently asked questions ### What does Making Memory Chips Faster by Splitting Internal Wires cover? This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. ### When does this patent expire? This patent is expected to expire on September 15, 2046, when the invention enters the public domain. ### What problem does this patent solve? The speed of memory directly impacts how fast computers, phones, and other devices can operate. This patent addresses a fundamental physical limitation in memory design: the parasitic capacitance on bit-lines that slows down data access. By reducing this capacitance, the technology described could lead to faster, more power-efficient memory components, which are crucial for everything from high-performance computing to everyday consumer electronics. ### What does this patent NOT cover? Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting. **Full plain-English explainer:** https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance **Original patent:** https://patents.google.com/patent/US12740066 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Save Memory Power by Grouping Error-Correction Data](https://patentbrief.org/patent/us/12321234/raptor-2) — A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - [How a Special Memory Chip Helps Fix Broken 3D NAND Storage](https://patentbrief.org/patent/us/12450117/firmware-repair-for-three-dimensional-nand-memory) — This patent describes a special content addressable memory (CAM) system that quickly finds and reroutes around defective memory locations in 3D NAND storage using multiple processing units at once. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming. - [How to Precisely Erase Data in 3D NAND Flash Memory](https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory) — This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed.