{
  "patent_number": "US 12740066",
  "country": "US",
  "title": "Making Memory Chips Faster by Splitting Internal Wires",
  "original_title": "Split memory array to reduce bit-line capacitance",
  "summary": "This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access.",
  "what_it_does": "This patent describes a way to improve memory performance by splitting a memory array into two or more smaller sections, called subarrays. It uses special electronic switches, called bit-line multiplexers or selection circuitries, to divide the bit-line routes between these subarrays. By decoupling the bit-lines in this manner, the electrical charge-storing ability, known as capacitance, on the bit-lines is significantly reduced. This reduction comes from decreasing unwanted parasitic capacitance and ensuring that a single bit-line doesn't have to power all the tiny switches (access transistors) in a memory row. For example, when reading data from a specific memory cell, only the relevant split bit-line segment is activated, allowing the electrical signal to develop faster and stronger, which leads to quicker data sensing and overall higher memory performance.",
  "what_it_does_not_cover": [
    "Does not cover memory designs that use a single, unbroken bit-line stretching across an entire memory array without splitting.",
    "Does not cover methods for reducing memory capacitance that do not involve splitting bit-lines with selection circuitries.",
    "Does not cover improvements to memory speed achieved solely by optimizing access transistor switching without modifying bit-line architecture.",
    "Does not cover memory architectures that do not rely on bit-lines for data transfer to and from memory cells."
  ],
  "filed": "2022-07-12",
  "granted": "2026-09-15",
  "expires": null,
  "status": "active",
  "holder": null,
  "holder_url": null,
  "inventors": [],
  "times_cited": 0,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications"
  ],
  "abstract": "A memory array is split into two or more subarrays with bit-line multiplexers or selection circuitries between the subarrays. Bit-line routes are split along the subarrays via the selection circuitries. The selection circuitries decouple the bit-lines into separate bit-line routes which allow the capacitance on the bit-lines to reduce as parasitic capacitance from the bit-line routes is reduced and bit-line is not driving all the access transistors in a row of the memory array. By using one of the two split bit-lines as the main bit-line, the main bit-line has lower capacitance resulting in faster sensing and better sensing margin since the voltage for sensing on the bit-lines is developed faster, as also larger signal is developed due to lower parasitic capacitance. Further, the access transistor of the selected row can be switched faster which results in higher memory performance. Polarization density requirements also reduce by lowering the parasitic capacitance.",
  "url": "https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance",
  "markdown_url": "https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance/md",
  "google_patents_url": "https://patents.google.com/patent/US12740066",
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}