# How to Combine FPGA and Non-Volatile Memory Chips in One Package > This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive. - **Patent:** US 12737520 - **Original title:** Non-volatile programmable logic device based on multi-chip package - **Granted:** 2026 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, consumer_electronics, telecommunications, ai_ml, software ## What it does This patent describes a chip package designed as a logic drive. It includes multiple semiconductor chips, with a polymer layer placed horizontally between them. Over these chips and the polymer layer are multiple metal layers, which connect to the chips and extend across their edges. One of these metal layers has a thickness and trace width between 0.5 and 5 micrometers. Similarly, multiple dielectric layers are placed between the metal layers and also extend across the chip edges, with one dielectric layer having a thickness between 0.5 and 5 micrometers. The package uses metal bumps on its top metal layer for external connections. Crucially, one of the semiconductor chips is an FPGA IC chip, and another is a non-volatile memory (NVMIC) chip, enabling a programmable logic device with integrated persistent storage. ## What it does NOT cover - Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips. - Does not cover packages that combine different types of chips, such as a CPU and a GPU, as it specifically claims an FPGA and a NVMIC. - Does not cover packages where the metal or dielectric layers have thicknesses or trace widths outside the specified range of 0.5 to 5 micrometers. - Does not cover single-chip packages, as it explicitly requires multiple semiconductor chips. - Does not cover packages where the metal and dielectric layers do not extend across the edges of the semiconductor chips. ## The clever bit The clever bit is the precise structural integration of different chip types, specifically an FPGA and NVMIC, within a single package. This is achieved through a polymer layer horizontally separating chips, and finely dimensioned metal and dielectric layers that extend across the chip edges, enabling compact, high-speed interconnections and efficient power delivery for a logic drive. ## Real-world examples 1. System-in-Package (SiP) modules for embedded systems 2. Specialized computing modules for AI acceleration 3. Compact control units in industrial automation 4. FPGA-based network processing units with integrated configuration memory ## Why it matters Integrating Field-Programmable Gate Arrays (FPGAs) with non-volatile memory (NVM) in a single package is vital for modern electronics. FPGAs require configuration data, and NVM provides persistent storage for this data, allowing instant-on functionality and reducing boot times. This compact integration saves valuable board space, reduces power consumption, and improves performance by minimizing the distance between the FPGA and its configuration memory, which is critical for embedded systems and edge computing devices. ## Frequently asked questions ### What does How to Combine FPGA and Non-Volatile Memory Chips in One Package cover? This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive. ### When does this patent expire? This patent is expected to expire on September 15, 2046, when the invention enters the public domain. ### What problem does this patent solve? Integrating Field-Programmable Gate Arrays (FPGAs) with non-volatile memory (NVM) in a single package is vital for modern electronics. FPGAs require configuration data, and NVM provides persistent storage for this data, allowing instant-on functionality and reducing boot times. This compact integration saves valuable board space, reduces power consumption, and improves performance by minimizing the distance between the FPGA and its configuration memory, which is critical for embedded systems and edge computing devices. ### What does this patent NOT cover? Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips. **Full plain-English explainer:** https://patentbrief.org/patent/us/12737520/non-volatile-programmable-logic-device-based-on-multi-chip-package **Original patent:** https://patents.google.com/patent/US12737520 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Stack Two Computer Chips with Direct Connections](https://patentbrief.org/patent/us/9412678/structure-and-method-for-3d-ic-package) — TSMC's patent describes a compact way to stack two computer chips directly on top of each other, using a special filling material to hold tiny electrical connections in place, often with the top chip being wider than the bottom. - [How Chips Talk Fast with Light Inside a Circuit Board](https://patentbrief.org/patent/us/20260003141/package-having-component-carrier-and-embedded-optical-and-electric-chips-with-ho) — This patent describes a way to embed light-based (optical) and electricity-based (electric) computer chips directly next to each other within a circuit board, allowing them to communicate very quickly along a flat, horizontal path. - [How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate](https://patentbrief.org/patent/us/10181457/microelectronic-package-for-wafer-level-chip-scale-packaging-with-fan-out) — This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip. - [How Chips Get Both Light and Electricity on a Special Glass Base](https://patentbrief.org/patent/us/12326604/integrated-circuit-packages-having-electrical-and-optical-connectivity-and-metho) — This patent describes a way to build computer chip packages using a special glass base that can carry both electrical signals and light signals, making chips faster and more efficient. - [Stacking Chips with Light-Guiding Plastic Wires](https://patentbrief.org/patent/us/12181722/structures-and-process-flow-for-integrated-photonic-electric-ic-package-by-using) — TSMC's patent describes a method for building advanced chip packages that combine electrical and light-based circuits using polymer waveguides and an integrated fan-out redistribution layer for faster communication.