{
  "patent_number": "US 12737520",
  "country": "US",
  "title": "How to Combine FPGA and Non-Volatile Memory Chips in One Package",
  "original_title": "Non-volatile programmable logic device based on multi-chip package",
  "summary": "This patent describes a compact chip package that integrates multiple semiconductor chips, specifically an FPGA and a non-volatile memory chip, using precisely dimensioned metal and dielectric layers over a polymer layer for a logic drive.",
  "what_it_does": "This patent describes a chip package designed as a logic drive. It includes multiple semiconductor chips, with a polymer layer placed horizontally between them. Over these chips and the polymer layer are multiple metal layers, which connect to the chips and extend across their edges. One of these metal layers has a thickness and trace width between 0.5 and 5 micrometers. Similarly, multiple dielectric layers are placed between the metal layers and also extend across the chip edges, with one dielectric layer having a thickness between 0.5 and 5 micrometers. The package uses metal bumps on its top metal layer for external connections. Crucially, one of the semiconductor chips is an FPGA IC chip, and another is a non-volatile memory (NVMIC) chip, enabling a programmable logic device with integrated persistent storage.",
  "what_it_does_not_cover": [
    "Does not cover chip packages that do not include a polymer layer placed horizontally between the semiconductor chips.",
    "Does not cover packages that combine different types of chips, such as a CPU and a GPU, as it specifically claims an FPGA and a NVMIC.",
    "Does not cover packages where the metal or dielectric layers have thicknesses or trace widths outside the specified range of 0.5 to 5 micrometers.",
    "Does not cover single-chip packages, as it explicitly requires multiple semiconductor chips.",
    "Does not cover packages where the metal and dielectric layers do not extend across the edges of the semiconductor chips."
  ],
  "filed": "2023-03-24",
  "granted": "2026-09-15",
  "expires": null,
  "status": "active",
  "holder": null,
  "holder_url": null,
  "inventors": [],
  "times_cited": 0,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "ai_ml",
    "software"
  ],
  "abstract": "A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.",
  "url": "https://patentbrief.org/patent/us/12737520/non-volatile-programmable-logic-device-based-on-multi-chip-package",
  "markdown_url": "https://patentbrief.org/patent/us/12737520/non-volatile-programmable-logic-device-based-on-multi-chip-package/md",
  "google_patents_url": "https://patents.google.com/patent/US12737520",
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}