{
  "patent_number": "US 12737317",
  "country": "US",
  "title": "How Multiple Graphics Cards Keep Their Memory Caches Updated",
  "original_title": "Systems and methods for updating memory side caches in a multi-GPU configuration",
  "summary": "This patent describes methods for keeping the specialized memory caches of multiple graphics processing units (GPUs) consistent and up-to-date when they work together in a computer system.",
  "what_it_does": "This patent details a system for managing memory in computers with multiple graphics processing units (GPUs), often called a 'multi-tile architecture.' Each GPU has its own main memory, a fast 'memory side cache,' and a 'memory management unit' (MMU). These GPUs communicate through a 'communication fabric.' The core mechanism is that one GPU's MMU (e.g., the first MMU) is not only responsible for its own memory and cache updates but also determines if the 'memory side cache' of another GPU (e.g., the second memory side cache) needs to be updated. For example, if a high-performance computer uses two GPUs to render a complex scene, and one GPU updates a texture, its MMU checks if the other GPU's cache holds an outdated version of that texture and, if so, instructs it to refresh.",
  "what_it_does_not_cover": [
    "Does not cover systems with only a single graphics processing unit (GPU).",
    "Does not cover systems where a central processing unit (CPU) or other non-GPU component solely manages cross-GPU cache coherence.",
    "Does not cover multi-GPU systems that do not employ 'memory side caches' as described.",
    "Does not cover systems where each GPU's cache is updated entirely independently without coordination from another GPU's MMU.",
    "Does not cover multi-GPU setups that lack a 'communication fabric' for direct GPU-to-GPU data exchange."
  ],
  "filed": "2023-11-21",
  "granted": "2026-09-15",
  "expires": null,
  "status": "active",
  "holder": null,
  "holder_url": null,
  "inventors": [],
  "times_cited": 0,
  "tags": [
    "consumer_electronics",
    "semiconductors",
    "ai_ml",
    "high_performance_computing"
  ],
  "abstract": "Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.",
  "url": "https://patentbrief.org/patent/us/12737317/systems-and-methods-for-updating-memory-side-caches-in-a-multi-gpu-configuration",
  "markdown_url": "https://patentbrief.org/patent/us/12737317/systems-and-methods-for-updating-memory-side-caches-in-a-multi-gpu-configuration/md",
  "google_patents_url": "https://patents.google.com/patent/US12737317",
  "relatedPatents": []
}