# How to Save Memory Power by Grouping Error-Correction Data > A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. - **Patent:** US 12321234 - **Original title:** Energy efficient storage of error-correction-detection information - **Owner:** Rambus Inc - **Granted:** 2025 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, telecommunications, ai_ml ## What it does This patent describes a memory controller that optimizes how it retrieves error-correction information. Traditionally, a controller might trigger a separate row access for every data channel's error-checking bits, which consumes significant power. This design groups check bits for multiple data rows into a single row within an error-correction memory component. When the controller accesses one data row, it simultaneously opens the error-correction row, fetches the necessary check bits, and caches the remaining check bits for future use. This reduces the total number of row activations required to verify data integrity. ## What it does NOT cover - Does not cover memory systems that use a single channel for both data and error-correction information. - Does not cover software-based error correction algorithms that run on a CPU. - Does not cover systems where error-correction bits are stored within the same physical row as the data they protect. ## The clever bit The innovation lies in pre-fetching and caching 'future' check bits while the error-correction row is already open for a current request, effectively turning one row access into a multi-purpose operation. ## Real-world examples 1. Enterprise server memory controllers 2. High-performance computing (HPC) memory subsystems 3. Data center DRAM interfaces ## Why it matters In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations. ## Frequently asked questions ### What does How to Save Memory Power by Grouping Error-Correction Data cover? A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. ### Who owns patent US 12321234? Rambus Inc owns this patent, granted in 2025. ### When does this patent expire? This patent is expected to expire on June 3, 2045, when the invention enters the public domain. ### What problem does this patent solve? In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations. ### What does this patent NOT cover? Does not cover memory systems that use a single channel for both data and error-correction information. **Full plain-English explainer:** https://patentbrief.org/patent/us/12321234/raptor-2 **Original patent:** https://patents.google.com/patent/US12321234 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How NAND Flash Memory Adjusts to Cold Temperatures](https://patentbrief.org/patent/us/10019188/storage-devices-memory-systems-and-operating-methods-to-suppress-operating-error) — This patent describes a method for NAND flash memory systems to prevent errors by automatically adjusting their operating conditions, like data speed or voltage, when the temperature drops too low. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming. - [How a Chip Uses Memory to Speed Up AI Calculations](https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network) — This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information. - [How IBM's Storage Controllers Keep Data Backups in the Right Order](https://patentbrief.org/patent/us/5682513/cache-queue-entry-linking-for-dasd-record-updates) — A method for storage controllers to track and sequence data updates in a specific order, ensuring that remote backups remain consistent with the original data during a system failure. - [How to Send Data Streams Independently Without Connection Overload](https://patentbrief.org/patent/us/7904576/reliable-datagram-via-independent-source-destination-resources) — A method for sending multiple streams of data between devices using independent, reliable paths that keep data in the correct order without needing a constant connection.