# How to Save Memory Power by Grouping Error-Correction Data > A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. - **Patent:** US 12321234 - **Original title:** Energy efficient storage of error-correction-detection information - **Owner:** Rambus Inc - **Granted:** 2025 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, telecommunications, ai_ml ## What it does This patent describes a memory controller that optimizes how it retrieves error-correction information. Traditionally, a controller might trigger a separate row access for every data channel's error-checking bits, which consumes significant power. This design groups check bits for multiple data rows into a single row within an error-correction memory component. When the controller accesses one data row, it simultaneously opens the error-correction row, fetches the necessary check bits, and caches the remaining check bits for future use. This reduces the total number of row activations required to verify data integrity. ## What it does NOT cover - Does not cover memory systems that use a single channel for both data and error-correction information. - Does not cover software-based error correction algorithms that run on a CPU. - Does not cover systems where error-correction bits are stored within the same physical row as the data they protect. ## The clever bit The innovation lies in pre-fetching and caching 'future' check bits while the error-correction row is already open for a current request, effectively turning one row access into a multi-purpose operation. ## Real-world examples 1. Enterprise server memory controllers 2. High-performance computing (HPC) memory subsystems 3. Data center DRAM interfaces ## Why it matters In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations. ## Frequently asked questions ### What does How to Save Memory Power by Grouping Error-Correction Data cover? A method for memory controllers to reduce power consumption by fetching multiple sets of error-checking data in a single memory row access instead of one-by-one. ### Who owns patent US 12321234? Rambus Inc owns this patent, granted in 2025. ### When does this patent expire? This patent is expected to expire on June 3, 2045, when the invention enters the public domain. ### What problem does this patent solve? In large-scale data centers and high-performance computing, memory power consumption is a major operational cost. By reducing the number of row activations—a power-intensive operation—this technology helps lower the thermal and electrical footprint of massive memory arrays. It is particularly relevant for modern server architectures that rely on high-bandwidth, multi-channel memory configurations. ### What does this patent NOT cover? Does not cover memory systems that use a single channel for both data and error-correction information. **Full plain-English explainer:** https://patentbrief.org/patent/us/12321234/raptor-2 **Original patent:** https://patents.google.com/patent/US12321234 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How Memory Devices Dynamically Manage Overly Busy Data Rows](https://patentbrief.org/patent/us/12737123/apparatuses-and-methods-for-aggressor-queue-based-mitigation-threshold) — This patent describes a method for memory devices to identify and manage frequently accessed data rows by dynamically adjusting a threshold based on how many such 'aggressor rows' are already detected. - [Making Memory Chips Faster by Splitting Internal Wires](https://patentbrief.org/patent/us/12740066/split-memory-array-to-reduce-bit-line-capacitance) — This patent describes a method to make computer memory faster and more efficient by dividing its internal wiring into smaller sections, which reduces electrical interference and speeds up data access. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - [Making Computer Caches Faster with Dynamic Overfetching](https://patentbrief.org/patent/us/12737318/cache-structure-and-utilization) — This patent describes a method for computer processors to speed up by intelligently fetching more data than immediately needed into a temporary storage area called a cache, especially when requested data isn't found. - [How Multiple Graphics Cards Keep Their Memory Caches Updated](https://patentbrief.org/patent/us/12737317/systems-and-methods-for-updating-memory-side-caches-in-a-multi-gpu-configuration) — This patent describes methods for keeping the specialized memory caches of multiple graphics processing units (GPUs) consistent and up-to-date when they work together in a computer system.