# How to Precisely Erase Data in 3D NAND Flash Memory > This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. - **Patent:** US 12142328 - **Original title:** Erasing and erasing verification for three-dimensional NAND memory - **Owner:** Yangtze Memory Technologies Co - **Granted:** 2024 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, consumer_electronics, telecommunications, software ## What it does This patent details a method for erasing memory cells in a 3D NAND device more precisely. First, a relatively large "first erase voltage" is applied and gradually increased by a "first erase step voltage" until the memory cells pass an "initial erase verification" (Claim 1). This is a coarse erase. After this initial pass, the system performs several "sub-erase verifications" using different "sub-erase verification voltages" to check the erase state more closely (Claim 1, Claim 6). Based on whether the cells pass or fail these sub-verifications, a "second erase voltage" is applied. This second voltage is increased by a much smaller "second erase step voltage," which is dynamically adjusted by the sub-verification results (Claim 1, Claim 9). This fine-tuning ensures a more accurate and complete erase. For example, if a cell is almost erased but not quite, the sub-verifications help determine the exact small voltage boost needed. ## What it does NOT cover - Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step. - Does not cover memory erase processes for types of memory other than 3D NAND, such as DRAM or NOR flash. - Does not cover erase verification methods that do not involve incrementally increasing an erase voltage in two distinct stages with different step sizes. - Does not cover methods where the second erase step voltage is not determined by the results of intermediate sub-erase verifications. - Does not cover memory devices that do not have a control circuit configured to perform these specific erase and verification steps. ## The clever bit The clever part is the two-stage erase process with adaptive fine-tuning. It uses a larger voltage step for initial erasing, then switches to much smaller, dynamically adjusted voltage steps based on detailed sub-verifications. This allows for a precise erase without wasting cycles or overstressing the memory cells. ## Real-world examples 1. Solid-state drives (SSDs) in computers 2. Smartphones and tablets with internal storage 3. USB flash drives 4. Enterprise data center storage arrays 5. Memory cards for cameras and other devices ## Why it matters NAND flash memory is crucial for storing data in many devices, from smartphones to data centers. Efficient and reliable erasing is vital for memory longevity and performance. This method aims to prevent over-erasing, which can damage cells, and under-erasing, which leaves residual data. By fine-tuning the erase process, it helps extend the lifespan of 3D NAND memory and improve its reliability. ## Frequently asked questions ### What does How to Precisely Erase Data in 3D NAND Flash Memory cover? This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed. ### Who owns patent US 12142328? Yangtze Memory Technologies Co owns this patent, granted in 2024. ### When does this patent expire? This patent is expected to expire on September 22, 2042, when the invention enters the public domain. ### What problem does this patent solve? NAND flash memory is crucial for storing data in many devices, from smartphones to data centers. Efficient and reliable erasing is vital for memory longevity and performance. This method aims to prevent over-erasing, which can damage cells, and under-erasing, which leaves residual data. By fine-tuning the erase process, it helps extend the lifespan of 3D NAND memory and improve its reliability. ### What does this patent NOT cover? Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step. **Full plain-English explainer:** https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory **Original patent:** https://patents.google.com/patent/US12142328 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How to Program 3D Layered Memory Chips More Precisely](https://patentbrief.org/patent/us/9947413/method-of-initializing-and-programming-3d-non-volatile-memory-device) — This patent describes a method for precisely programming the control transistors and memory cells in advanced 3D non-volatile memory chips, ensuring reliable data storage in stacked layers. - [How to Prepare 3D Flash Memory for Use](https://patentbrief.org/patent/us/9685235/method-of-initializing-3d-non-volatile-memory-device) — This patent describes a method for setting up a 3D non-volatile memory chip, like those in SSDs, by precisely programming control transistors, including a special "dummy" one, to make sure the memory works correctly. - [How 3D Memory Chips Fix Tiny Flaws to Keep Working](https://patentbrief.org/patent/us/9263111/sub-block-disabling-in-3d-memory) — Micron's 2016 patent describes how 3D NAND memory chips can identify and turn off small, defective sections (sub-blocks) to extend the life of the entire memory block, rather than discarding the whole chip. - [How Flash Memory Cells Use an Erase Gate to Clear Data](https://patentbrief.org/patent/us/4531203/nand-flash-memory) — This 1985 patent describes the foundational structure of flash memory, introducing an 'erase gate' that allows data to be electrically wiped from a memory cell. - [How Multi-Level Cell Memory Stores More Data in Less Space](https://patentbrief.org/patent/us/5903495/semiconductor-device-and-memory-system) — Toshiba's 1999 patent describes a method for storing multiple bits of data in a single memory cell by precisely controlling voltage levels during programming.