{
  "patent_number": "US 12142328",
  "country": "US",
  "title": "How to Precisely Erase Data in 3D NAND Flash Memory",
  "original_title": "Erasing and erasing verification for three-dimensional NAND memory",
  "summary": "This patent describes a two-stage method for erasing data in 3D NAND memory, using a coarse erase followed by a fine-tuned erase based on multiple sub-verifications to ensure data is completely and efficiently removed.",
  "what_it_does": "This patent details a method for erasing memory cells in a 3D NAND device more precisely. First, a relatively large \"first erase voltage\" is applied and gradually increased by a \"first erase step voltage\" until the memory cells pass an \"initial erase verification\" (Claim 1). This is a coarse erase. After this initial pass, the system performs several \"sub-erase verifications\" using different \"sub-erase verification voltages\" to check the erase state more closely (Claim 1, Claim 6). Based on whether the cells pass or fail these sub-verifications, a \"second erase voltage\" is applied. This second voltage is increased by a much smaller \"second erase step voltage,\" which is dynamically adjusted by the sub-verification results (Claim 1, Claim 9). This fine-tuning ensures a more accurate and complete erase. For example, if a cell is almost erased but not quite, the sub-verifications help determine the exact small voltage boost needed.",
  "what_it_does_not_cover": [
    "Does not cover erase methods that do not use an initial coarse erase step followed by a finer, adaptively adjusted erase step.",
    "Does not cover memory erase processes for types of memory other than 3D NAND, such as DRAM or NOR flash.",
    "Does not cover erase verification methods that do not involve incrementally increasing an erase voltage in two distinct stages with different step sizes.",
    "Does not cover methods where the second erase step voltage is not determined by the results of intermediate sub-erase verifications.",
    "Does not cover memory devices that do not have a control circuit configured to perform these specific erase and verification steps."
  ],
  "filed": "2022-09-22",
  "granted": "2024-11-12",
  "expires": "2042-09-22",
  "status": "active",
  "holder": "Yangtze Memory Technologies Co",
  "holder_url": "https://patentbrief.org/company/yangtze-memory-technologies-co",
  "inventors": [
    {
      "name": "Kaijin Huang",
      "url": "https://patentbrief.org/inventor/kaijin-huang"
    }
  ],
  "times_cited": 0,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "software"
  ],
  "abstract": "The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.",
  "url": "https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory",
  "markdown_url": "https://patentbrief.org/patent/us/12142328/erasing-and-erasing-verification-for-three-dimensional-nand-memory/md",
  "google_patents_url": "https://patents.google.com/patent/US12142328",
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}