{
  "patent_number": "US 11741188",
  "country": "US",
  "title": "How a Chip Uses Memory to Speed Up AI Calculations",
  "original_title": "Hardware accelerated discretized neural network",
  "summary": "This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information.",
  "what_it_does": "This patent describes a device and method for speeding up neural network calculations using specialized hardware. It starts by converting digital input signals into analog signals using a Digital-to-Analog Converter (DAC). These analog signals then go into non-volatile memory (NVM) weight arrays, which perform complex math called vector matrix multiplication (VMM). A key part is that each \"synaptic weight element\" (like a connection strength in a brain model) is represented by multiple parallel NVM cells, such as at least three parallel NVM cells (Claim 4, 13), which helps with accuracy. After the VMM, Analog-to-Digital Converters (ADCs) turn the analog results back into digital values. A \"neural circuit\" then processes these digital values, applying activation functions to calculate a \"new memory cell state\" (Claim 1, 10), which can be fed back for the next calculation cycle, useful for AI that processes sequences like language.",
  "what_it_does_not_cover": [
    "Does not cover neural network computations performed entirely in the digital domain without analog conversion.",
    "Does not cover systems where synaptic weight elements are represented by a single NVM cell, as it specifies \"multiple parallel NVM cells\" (Claim 1, 10).",
    "Does not cover VMM computations performed using volatile memory (like DRAM or SRAM) instead of non-volatile memory (NVM) weight arrays.",
    "Does not cover systems that do not convert digital input signals to analog for VMM computation.",
    "Does not cover systems that do not convert analog VMM results back to digital values using ADCs."
  ],
  "filed": "2021-07-08",
  "granted": "2023-08-29",
  "expires": "2041-07-08",
  "status": "active",
  "holder": "Western Digital Technologies",
  "holder_url": "https://patentbrief.org/company/western-digital-technologies",
  "inventors": [
    {
      "name": "Pi-Feng Chiu",
      "url": "https://patentbrief.org/inventor/pi-feng-chiu"
    },
    {
      "name": "Won Ho Choi",
      "url": "https://patentbrief.org/inventor/won-ho-choi"
    },
    {
      "name": "Martin LUEKER-BODEN",
      "url": "https://patentbrief.org/inventor/martin-lueker-boden"
    },
    {
      "name": "Minghai Qin",
      "url": "https://patentbrief.org/inventor/minghai-qin"
    },
    {
      "name": "Wen Ma",
      "url": "https://patentbrief.org/inventor/wen-ma"
    }
  ],
  "times_cited": 0,
  "tags": [
    "consumer_electronics",
    "software",
    "semiconductors",
    "ai_ml",
    "telecommunications"
  ],
  "abstract": "An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.",
  "url": "https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network",
  "markdown_url": "https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network/md",
  "google_patents_url": "https://patents.google.com/patent/US11741188",
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}