# Making AI Chips Faster with Multiple Readers for Stored Data > This patent describes a specialized computer chip design that uses multiple reading components for each stored piece of information, allowing artificial intelligence calculations to happen much faster and more efficiently. - **Patent:** US 11087204 - **Original title:** Resistive processing unit with multiple weight readers - **Owner:** International Business Machines - **Granted:** 2021 - **Status:** Active - **Times cited:** 0 - **Field:** semiconductors, ai_ml, consumer_electronics, telecommunications ## What it does This patent describes a "crossbar array" of tiny processing units, called "resistive processing unit (RPU) devices," each located at a "crosspoint." Each RPU device holds a "single weight storage element" that stores a value, but critically, it has "multiple weight reader elements" (Claim 1). A first reader connects to a "first row wire" to calculate a "first matrix product value" using an incoming value and the stored value. Simultaneously, a second reader connects to a "second row wire" to calculate a "second matrix product value" using a different incoming value and the *same* stored value (Claim 1). This design allows the RPU devices to compute these matrix product values "concurrently" (Claim 6), meaning at the same time, which speeds up complex calculations. For example, in an AI system recognizing an object, this chip could process multiple features of an image against its learned knowledge simultaneously. ## What it does NOT cover - Does not cover RPU devices where each stored value is read by only a single reader element. - Does not cover RPU devices where each crosspoint has multiple weight storage elements instead of a single one. - Does not cover processing units that are not 'resistive' in nature, focusing specifically on a resistive architecture. - Does not cover general-purpose computing or mathematical operations other than matrix product calculations. ## The clever bit The truly clever part is the design choice to have multiple independent 'reader' components for a *single* piece of stored data within each processing unit. This allows the system to perform several calculations using the same stored value at the exact same time, avoiding the need to duplicate data or wait for sequential access. ## Real-world examples 1. Specialized AI accelerator chips 2. Neuromorphic computing hardware 3. Hardware for deep learning inference 4. High-performance computing for AI training ## Why it matters Artificial intelligence and machine learning rely heavily on complex mathematical operations, especially matrix multiplication, which can be very time-consuming. This patent aims to make these core calculations much faster and more energy-efficient by allowing multiple parts of a calculation to happen at the same time within a single processing unit. This kind of innovation is crucial for developing more powerful AI models and deploying them in real-world applications, from self-driving cars to advanced medical diagnostics. ## Frequently asked questions ### What does Making AI Chips Faster with Multiple Readers for Stored Data cover? This patent describes a specialized computer chip design that uses multiple reading components for each stored piece of information, allowing artificial intelligence calculations to happen much faster and more efficiently. ### Who owns patent US 11087204? International Business Machines owns this patent, granted in 2021. ### When does this patent expire? This patent is expected to expire on April 20, 2038, when the invention enters the public domain. ### What problem does this patent solve? Artificial intelligence and machine learning rely heavily on complex mathematical operations, especially matrix multiplication, which can be very time-consuming. This patent aims to make these core calculations much faster and more energy-efficient by allowing multiple parts of a calculation to happen at the same time within a single processing unit. This kind of innovation is crucial for developing more powerful AI models and deploying them in real-world applications, from self-driving cars to advanced medical diagnostics. ### What does this patent NOT cover? Does not cover RPU devices where each stored value is read by only a single reader element. **Full plain-English explainer:** https://patentbrief.org/patent/us/11087204/resistive-processing-unit-with-multiple-weight-readers **Original patent:** https://patents.google.com/patent/US11087204 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How a Single Electronic Component Can Learn and Process AI Data](https://patentbrief.org/patent/us/10248907/resistive-processing-unit) — This patent describes a tiny electronic component called a resistive processing unit (RPU) that acts like a brain cell in an artificial intelligence network, storing and processing information directly within its changing electrical resistance. - [How IBM Uses Resistive Memory Chips to Speed Up AI Training](https://patentbrief.org/patent/us/10740671/convolutional-neural-networks-using-resistive-processing-unit-array) — A method for running AI neural networks directly on specialized hardware chips that store data as electrical resistance, making them faster and more energy-efficient than standard processors. - [Training AI Chips Using Memristor Crossbars Directly On-Chip](https://patentbrief.org/patent/us/20230409893/on-chip-training-of-memristor-crossbar-neuromorphic-processing-systems) — This patent describes an electronic circuit that uses special memory components called memristors to train artificial intelligence models directly on the chip, making them learn more efficiently. - [How to Fix Faulty Memory Cells in AI Chips](https://patentbrief.org/patent/us/10956815/killing-asymmetric-resistive-processing-units-for-neural-network-training) — This patent describes a system that tests individual memory cells in AI chips for uneven behavior and then permanently disables the faulty ones before the chip starts learning, making AI training more efficient. - [How a Chip Uses Memory to Speed Up AI Calculations](https://patentbrief.org/patent/us/11741188/hardware-accelerated-discretized-neural-network) — This patent describes a specialized computer chip that uses non-volatile memory and analog signals to quickly perform calculations for artificial intelligence, especially for neural networks that need to remember past information.