# How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate > This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip. - **Patent:** US 10181457 - **Original title:** Microelectronic package for wafer-level chip scale packaging with fan-out - **Owner:** Invensas - **Granted:** 2019 - **Status:** Active - **Times cited:** 13 - **Field:** semiconductors, consumer_electronics, telecommunications, automotive ## What it does Claim 1 describes a 'package-on-package device' that uses a 'metal substrate' with distinct 'outer conductive pads' and 'inner conductive pads'. A 'microelectronic device' connects to the 'inner conductive pads' via 'first interconnects', which can be 'posts' (Claim 4). 'Wire bond wires' attach to the 'outer conductive pads'. A 'redistribution layer' on the lower surface connects these pads. The key feature is that the 'outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device' (Claim 1). This allows connections to spread out beyond the chip's footprint. For example, a processor chip could be connected to memory chips stacked above it, with all connections efficiently routed to a larger circuit board below. ## What it does NOT cover - Does not cover chip packages that do not use a metal substrate as the base (Claim 1). - Does not cover single-chip packages; it specifically claims a 'package-on-package device' (Claim 1). - Does not cover packaging where electrical connections do not 'fan-out' beyond the microelectronic device's perimeter (Claim 1). - Does not cover packages that connect chips without using both 'wire bond wires' and 'first interconnects' (posts) as described (Claim 1, 4). - Does not cover packages without a 'redistribution layer' connecting the pads on the lower surface (Claim 1). ## The clever bit The novelty lies in combining a metal substrate with electrically isolated inner and outer conductive pads, specifically designed for a 'package-on-package' configuration. This setup allows for efficient 'fan-out' of connections from both wire bonds and stacked chips, maximizing connectivity in a minimal footprint. ## Real-world examples 1. Smartphones 2. Wearable electronics 3. Internet of Things (IoT) devices 4. High-density memory modules 5. Automotive electronics control units ## Why it matters This technology is crucial for making smaller, more powerful electronic devices. By enabling the stacking of multiple chips (like a processor and memory) in a 'package-on-package' arrangement, it saves valuable space inside devices. The 'fan-out' capability allows for more electrical connections in a compact area, which is essential for high-performance chips in modern smartphones, wearables, and other miniaturized electronics. ## Frequently asked questions ### What does How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate cover? This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip. ### Who owns patent US 10181457? Invensas owns this patent, granted in 2019. ### When does this patent expire? This patent is expected to expire on October 24, 2036, when the invention enters the public domain. ### What is patent US 10181457 cited by? This patent has been cited by 13 later patents that build on its ideas. ### What problem does this patent solve? This technology is crucial for making smaller, more powerful electronic devices. By enabling the stacking of multiple chips (like a processor and memory) in a 'package-on-package' arrangement, it saves valuable space inside devices. The 'fan-out' capability allows for more electrical connections in a compact area, which is essential for high-performance chips in modern smartphones, wearables, and other miniaturized electronics. ### What does this patent NOT cover? Does not cover chip packages that do not use a metal substrate as the base (Claim 1). **Full plain-English explainer:** https://patentbrief.org/patent/us/10181457/microelectronic-package-for-wafer-level-chip-scale-packaging-with-fan-out **Original patent:** https://patents.google.com/patent/US10181457 --- _Source: PatentBrief — https://patentbrief.org. Patent facts are from public records; the plain-English explanation is PatentBrief's._ ## Related patents Semantically similar inventions in the PatentBrief corpus: - [How Chips Are Stacked and Wired in Tiny Phone Parts](https://patentbrief.org/patent/us/8310051/package-on-package-with-fan-out-wlcsp) — MediaTek's 2012 patent describes a way to stack different types of computer chips, like a processor and memory, very closely together in a single package using special wiring that spreads out connections, saving space in devices like smartphones. - [How to Stack Computer Chips on a Wafer for Smaller Devices](https://patentbrief.org/patent/us/7824959/wafer-level-stack-structure-for-system-in-package-and-method-thereof) — This patent describes a method for stacking two full wafers of computer chips, where the chips on each wafer are roughly the same overall size but have different active areas, to create a compact system-in-package. - [How to Stack Two Computer Chips with Direct Connections](https://patentbrief.org/patent/us/9412678/structure-and-method-for-3d-ic-package) — TSMC's patent describes a compact way to stack two computer chips directly on top of each other, using a special filling material to hold tiny electrical connections in place, often with the top chip being wider than the bottom. - [Connecting Computer Chips with a Special Bridge Die](https://patentbrief.org/patent/us/7969009/through-silicon-via-bridge-interconnect) — This patent describes a system for connecting multiple computer chips side-by-side using a third, 'bridge' chip that has vertical tunnels (TSVs) to link them together. - [How Chips Get Both Light and Electricity on a Special Glass Base](https://patentbrief.org/patent/us/12326604/integrated-circuit-packages-having-electrical-and-optical-connectivity-and-metho) — This patent describes a way to build computer chip packages using a special glass base that can carry both electrical signals and light signals, making chips faster and more efficient.