{
  "patent_number": "US 10181457",
  "country": "US",
  "title": "How a Fan-Out Chip Package Connects Multiple Chips on a Metal Substrate",
  "original_title": "Microelectronic package for wafer-level chip scale packaging with fan-out",
  "summary": "This patent describes a way to stack and connect multiple tiny computer chips using a metal base, allowing more connections to spread out from the chip.",
  "what_it_does": "Claim 1 describes a 'package-on-package device' that uses a 'metal substrate' with distinct 'outer conductive pads' and 'inner conductive pads'. A 'microelectronic device' connects to the 'inner conductive pads' via 'first interconnects', which can be 'posts' (Claim 4). 'Wire bond wires' attach to the 'outer conductive pads'. A 'redistribution layer' on the lower surface connects these pads. The key feature is that the 'outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device' (Claim 1). This allows connections to spread out beyond the chip's footprint. For example, a processor chip could be connected to memory chips stacked above it, with all connections efficiently routed to a larger circuit board below.",
  "what_it_does_not_cover": [
    "Does not cover chip packages that do not use a metal substrate as the base (Claim 1).",
    "Does not cover single-chip packages; it specifically claims a 'package-on-package device' (Claim 1).",
    "Does not cover packaging where electrical connections do not 'fan-out' beyond the microelectronic device's perimeter (Claim 1).",
    "Does not cover packages that connect chips without using both 'wire bond wires' and 'first interconnects' (posts) as described (Claim 1, 4).",
    "Does not cover packages without a 'redistribution layer' connecting the pads on the lower surface (Claim 1)."
  ],
  "filed": "2016-10-24",
  "granted": "2019-01-15",
  "expires": "2036-10-24",
  "status": "active",
  "holder": "Invensas",
  "holder_url": "https://patentbrief.org/company/invensas",
  "inventors": [
    {
      "name": "Rajesh Katkar",
      "url": "https://patentbrief.org/inventor/rajesh-katkar"
    },
    {
      "name": "Ashok S. Prabhu",
      "url": "https://patentbrief.org/inventor/ashok-s-prabhu"
    }
  ],
  "times_cited": 13,
  "tags": [
    "semiconductors",
    "consumer_electronics",
    "telecommunications",
    "automotive"
  ],
  "abstract": "Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.",
  "url": "https://patentbrief.org/patent/us/10181457/microelectronic-package-for-wafer-level-chip-scale-packaging-with-fan-out",
  "markdown_url": "https://patentbrief.org/patent/us/10181457/microelectronic-package-for-wafer-level-chip-scale-packaging-with-fan-out/md",
  "google_patents_url": "https://patents.google.com/patent/US10181457",
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}